Hetero-epitaxial growth of a semiconducting material, e.g., silicon germanium (SiGe) or germanium (Ge), on another semiconducting material, e.g., silicon (Si), often results in defects, for instance dislocations, due to, for instance, the mismatch in lattice constants.
Growth in confined spaces, as performed with the technique of Aspect Ratio Trapping (ART), can reduce defects that are growing near the edges of the confined space (e.g., towards a shallow trench isolation (STI)). See, e.g., Bai, J. et al., Study of the defect elimination mechanisms in aspect ratio trapping Ge growth, Applied Physics Letters, Volume 90, Issue 10, ID. 101902 (2007). This technique does not provide a solution for reducing defects as for instance dislocations near the center of the active device or active device layer. The presence of defects, as for instance dislocations, in an active device layer, as for instance a channel layer of a transistor device, is especially a concern for FinFETs and similar devices, wherein high mobility channel materials are integrated onto Silicon wafers.